1. Field of the Invention
The present invention relates to an automatic design technology for an LSI by use of a computer.
2. Description of the Related Art
Semiconductor chips such as LSIs have tended to increase integration scales and sizes in recent years. Furthermore, clock frequencies supplied to those LSI circuits have been drastically enhanced. In this connection, power dissipation by a semiconductor chip is also increasing. For this reason, when an LSI circuit is loaded on a portable device using a battery as a power source, operating time of such a portable device per of the battery is decreased. Accordingly, reduction in power dissipation by the circuit is demanded.
One of methods for achieving reduction in power dissipation is to reduce glitches that occur in a circuit. A “glitch” refers to an electrical noise which is caused by switching. Electric power consumed by a glitch is only a waste of power; accordingly, it is desirable to minimize such glitches.
A method for reducing power dissipation attributable to glitches is to insert a latch into a combination circuit. In this method, even if a glitch is fed to a latch, the glitch does not appear in an output signal from the latch unless a clock signal is fed to the latch. Accordingly, the glitch can be excluded from the output signal from the latch. Eventually, it is possible to reduce power dissipation.
Another method for achieving reduction in power dissipation is the gated clock design. The gated clock design is a method for resolving a problem that power dissipation is considerably increased by supplying clock signals constantly to respective registers and therefore to the entire clock tree. According to the gated clock design, an enable circuit is insert between a clock and a register group. A clock signal is supplied to the register group only when a register-transfer condition is established while an output signal from the enable circuit has a certain value. In this event, an output signal from a logic circuit is received by the register group. According to the gated clock design, the register does not require a feedback loop for retaining a current value when the register-transfer condition is not established. Moreover, the frequency of the clock signals to be supplied to the register is reduced; accordingly, it is possible to reduce a frequency of the amplitude in the clock tree and thereby to reduce power dissipation.
Logic design occurs first in LSI design, then a placement process for respective gates is performed, and clock wiring is performed thereafter. Therefore, in the gated clock design as well, the logic design takes place first, then the placement process for respective gates corresponding to the logic design is performed, and a designing process for clock wiring to connect clock terminals of respective storage elements is performed thereafter. Here, the “storage elements” refer to all circuit elements capable of retaining values, for example, flip-flops (F/F), latches, and memories and the like. As one of the clock wiring processes, a clock tree synthesis (CTS) process may be used in order to minimize a clock skew. The CTS process is a process of wiring on latches mutually with the same wiring distances and in a bottom-up manner. The CTS processing equalizes propagation delays of clock signals reaching the respective clock terminals. As a result, it is possible to achieve clock wiring while minimizing the clock skew.
However, the method of insertion the latches into the combination circuits requires insert of the latches into all the portions intended to reduce glitches. Accordingly, the method has a problem that the area of a semiconductor chip such as an LSI is increased due to insertion of the latches. As a result, such an increase in the area constitutes an obstacle for achieving a reduction in power dissipation.
Also, when the clock wiring is performed in the gated clock design by use of the CTS processing, it is possible that a timing constraint starting from the output signal from the F/F to the register group is not satisfied after the clock wiring. For example, consideration is given regarding a logic circuit adopting the gated clock design as shown in FIG. 1. Here, when a clock signal CLK is supplied to an enable circuit 103 through buffers 110 and 111, F/Fs 105 to 107, and wiring 150, 160 and 170, a register-transfer condition is established and an output signal from the enable circuit 103 is fed to an AND gate 101 through wiring 102, then the clock signal CLK is supplied from the AND gate 101 to register groups 104a and 104b through buffers 112a and 112b, and an output signal from a logic circuit 109 is received by the register groups 104a and 104b. Since the path delays starting from the F/Fs 105 to 107 to the output of the enable circuit 103 vary, it is possible that the timing constraints starting from the output signals from the F/Fs 105 to 107 to the register groups 104a and 104b are not satisfied after the clock wiring. Moreover, the buffers 112a and 112b may be added to an output destination of the AND gate 101, when the clock wiring is processed, in order to adjust a clock skew. In this case, propagation delays between the AND gate 101 and the register groups 104a and 104b are increased. Accordingly, a critical path not satisfying the timing constraint may be generated within the circuit in the region starting from the F/F 105 to 107 to the register groups 104a and 104b. In this case, it is necessary to return to the logic design and modify the logic design so as not to apply the gated clock design to the registers, and then to execute the placement process again. Such re-execution of the placement process incurs a problem of an increase in the designing time period.